The present invention relates to the field of semiconductor integrated circuits and, in particular, to an improved structure and method for making shallow trenches for isolation.
Shallow trench isolation (STI) is an essential part of current fabrication methods for microelectronic circuits. The decreasing dimensions of devices and the increasing density of integration in microelectronic circuits have required a corresponding reduction in the size of isolation structures. This reduction places a premium on reproducible formation of structures which provide effective isolation, while occupying a minimum amount of the substrate surface.
The STI technique is a widely used semiconductor fabrication method for forming isolation structures to electrically isolate the various active components formed in integrated circuits. In the STI technique, the first step is the formation of a plurality of trenches at predefined locations in the substrate, usually by anisotropic etching, followed by the deposition of an oxide into each of these trenches to form an STI structure. One major advantage of using the STI technique over the conventional LOCOS (Local Oxidation of Silicon) technique is the high scalability to CMOS (Complementary Metal-Oxide Semiconductor) IC devices for fabrication at the submicron level of integration. Another advantage is that the STI technique helps prevent the occurrence of the so-called bird""s beak encroachment, which is characteristic to the LOCOS technique for forming isolation structures.
Traditional STI fabrication methods have several drawbacks. One problem arises due to stress in the bottom of the trench. The rectangular corners formed at the bottom of STI trenches fabricated by traditional methods can lead to stress and dislocations in the isolation dielectric. This can further lead to current leakage paths and contaminants, which in turn reduce the effectiveness of the isolation structure. U.S. Pat. No. 5,956,598 provides a method for rounding the corners of STI structures, but the method described in this reference requires a high temperature anneal, which may not be compatible with the thermal budget of some fabrication processes.
Depth control of the isolation trench poses another problem. As shallower trenches become increasingly necessary or desirable, any process variability during trench formation takes on greater importance. As a result, dry etch processes, which have tolerable process variations for deeper trenches, become increasingly less acceptable for shallower trench structures.
A further limitation of the current art stems from the photolithography techniques. Isolation structures created by conventional STI methods have a minimum width that is determined by the resolution of current photolithography methods. Additionally, traditional STI methods are primarily designed for creation of trenches with a uniform, simple rectangular shape.
Accordingly, there is a need for an improved method for fabricating a shallow trench isolation region that reduces the stress in the trench structure without resorting to high temperature anneal steps. There is also needed a method for isolation that allows for reproducible creation of shallow trenches with a minimum of depth variation in the resulting trench structure, as well as a method of creating isolation structures that are narrower than current photolithographic resolution limits. A method for creating isolation structures with non-rectangular depth profiles is also desirable.
The present invention provides an improved method for creating shallow trench isolation structures. In one embodiment, a patterned mask is formed on a semiconductor substrate. The substrate is then subjected to dopant implantation to form highly doped regions in the non-masked portions of the substrate. After implantation, the highly doped regions are first anodized and then oxidized, leading to the formation of a porous oxide. This porous oxide is removed by a wet etching process, leaving behind a trench with exposed silicon. The trench is then oxidized and filled with a conventional suitable dielectric. The process produces a shallow trench with rounded corners which reduces mechanical stresses at the isolation region boundaries.
In another embodiment, a patterned hard mask is formed on a semiconductor substrate. The substrate is then subjected to a first dopant implantation, after which a spacer is formed on the patterned features of the mask. This results in a narrower mask feature. The wafer is then subjected to a second dopant implantation with a higher implantation energy. The resulting dopant profile in the substrate has a non-rectangular, tiered structure with a shallower, wider portion above a deeper, narrower portion. After both implantations, the highly doped regions are anodized and then oxidized, leading to the formation of porous oxide. This porous oxide is removed by a wet etching technique, leaving behind a trench with exposed silicon. The trench is then oxidized and filled with a conventional suitable dielectric. The isolation region again has rounded corners which reduce mechanical stresses at the isolation region boundaries.
In yet another embodiment, a patterned mask is formed on a semiconductor substrate, which has some of the pattern features at or near the resolution limit of the photolithography technique. A spacer is then formed on the patterned features of the mask and the substrate is subjected to a dopant implantation. Subsequently, highly doped regions, formed in the non-masked portions of the substrate, are anodized to become porous silicon regions. The porous silicon regions are then oxidized, forming regions of oxidized porous silicon. The porous oxide of the oxidized porous silicon regions is then removed by a wet etching, leaving behind trenches with exposed silicon surfaces. A preparation layer may be formed in these trenches, either by oxidizing the trenches or by depositing a thin dielectric layer in the trenches. In any case, the trenches are then filled with a conventional suitable dielectric. The isolation region again has rounded corners which reduce mechanical stresses at the isolation region boundaries.
In still another embodiment, a patterned mask is formed on a semiconductor substrate with optional spacers on the features of the patterned mask. If spacers are used, the mask must be a hard mask. The substrate is the subjected to an angled dopant implantation, at a fixed or varying angle, so that heavily doped regions with non-rectangular geometries are formed in the substrate. After implantation, the non-rectangular heavily doped regions are anodized to form porous silicon regions. The anodized regions are later oxidized to form a porous oxide. This porous oxide is then removed by a wet etching, leaving behind trenches with exposed silicon surfaces. The trenches are then filled with a conventional suitable dielectric. The isolation region again has rounded corners which reduce mechanical stresses at the isolation region boundaries.